1. Field of the Invention
The present invention relates to a testing apparatus and a testing method. Particularly, the present invention relates to a testing apparatus and a testing method for testing a memory under test.
2. Related Art
Generally, a memory testing apparatus applies address signals and data signals generated by a pattern generator to a memory under test to write the same thereon. Then, the memory testing apparatus compares expected value signals generated by the pattern generator corresponding to the address signals and the data signals and stores fail data indicating that an output signal is not matched with an expected value signal on an address fail memory (hereinafter referred to as AFM) in a fail analysis memory for each address indicated by the address signal. Then, the memory testing apparatus perform a fail safe analysis on the memory under test with reference to the fail data stored in the AFM as disclosed in, for example, Japanese Patent Application Publication No.10-556964.
FIG. 6 shows a flow of tests and fail safe analyses according to a related art. A type of memory testing apparatus as shown in FIG. 6A has a capacity comparable with the memory under test and performs a fail safe analysis by referring the AFM which sequentially stores fail data after testing the memory under test. Another type of memory testing apparatus as shown in FIG. 6B has a fail buffer memory (hereinafter referred to as FBM) having a capacity comparable with the memory under test in a fail safe analyzer in addition to the AFM, transfers fail data from AFM to FBM and performs the fail safe analysis of the previous test in parallel with performing a next test, so that the throughput of the test can be improved. Such memory testing apparatus is effective for the case that the transfer time of fail data is sufficiently less than a time for the fail safe analysis. However, as the transfer time of fail data is increased in associated with significantly increasing the capacity of the memory under test, the throughput can not have been improved. Therefore, it is necessary to reduce the transfer time of fail data. Thus, a memory testing apparatus, as shown in FIG. 6C has been proposed, that has two AFMs and performs a fail safe analysis by sequentially storing fail data during testing in one AFM in parallel with transferring the fail data of the previous test from the other AFM to a FBM.
In a manner of memory test in recent years, a memory under test is tested multiple times and a fail safe analysis is performed by accumulating the multiple times of test results. FIG. 7 shows a flow of tests and fail safe analyses according to the related art. Analysis 1 is an analysis of the test result of test 1. Analysis 1+2 is an analysis of test result by accumulating test 1 and test 2. Analysis 1+2+3 is an analysis of the test result by accumulating test 1, test 2 and test 3. The flows as shown in FIG. 7A and 7B have not improved the throughput of the test as the transfer time of fail data is increased in associated with significantly increasing the capacity of the memory under test. Additionally, in the flow as shown in FIG. 7C, a FBM has to accumulate the fail data transferred from the other a AFM on the fail data transferred from one AFM by a read-modify-write operation, so that it takes a large amount of processing time to transfer the fail data from the AFM to the FBM. Therefore, if the number of times for test is increased, a latency time is generated to transfer fail data from the AFM to the FBM. Therefore, the advantage of using two AFMs is lost.